srdatucsd (Member) asked a question.

ug575 & Vivado Ultrascale+ chip diagrams
It appears that Xilinx presents all the diagrams of where hard IP's and GTY's are located MIRRORED compared to actual PCB pin placement.  Seems to be a bottom view, but does not say so on each diagram.

Where in UG575 Vivado, or elsewhere is this stated?  If not, how is one to know?